LA72715NV-TLM-E【PDF 13/13 页】IC AUDIO DECODER JPN MTS 24SSOP

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Sheet目录2002

9页 10页 11页 12页 [13页]

LA72715NV

No.A1770-9/13

Continued from preceding page.

No.

Pin Name

DC voltage

AC level

Function

Equivalent Circuit

SLAVE ADD

SELECT

Line Out (R)

terminal

Line Out (L)

terminal

DC : 2.4V

AC : -4.5dBV

Line output pin.

250

Ω 300Ω

50k

2.5pF

PAD

VCC5V

MTS MODE

OUT

No signal

DC : 2.0V

Detection output for M.T.S. signal.

BILINGUAL

:3.0V

MONO

:2.0V

STEREO

:1.0V

10k

PAD

REG FILT

DC : 2.4V

Filter terminal of reference voltage source

10k

500

50k

500

PAD

2C BUS Serial Interface Specification

(1) Data Transfer Manual

This LSI adopts control method (I2C-BUS) with serial data, and controlled by two terminals which called SCL

(serial clock) and SDA (serial data). At first, set up*1the condition of starting data transfer, and after that, input 8 bit

data to SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale

of Bit), and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes ‘H’, this LSI

pull down the SDA terminal. After transferred the necessary data, two terminals lead to set up and of *2data transfer

stop condition, thus the transfer comes to close.

*1 Defined by SCL rise down SDA during ‘H’ period.

*2 Defined by SCL rise up SDA during ‘H’ period.

(2) Transfer Data Format

After transfer start condition, transfers slave address (1000 000*) to SDA terminal, control data, then, stop condition

(See figure 1).

Slave address is made up of 7bits, *38th bit shows the direction of transferring data, if it is ‘L’ takes write mode (As

this LSI side, this is input operation mode), and in case of ‘H’ reading mode (As this LSI side, this is output

operation mode).

Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be

canceled the transfer dates. At READ mode, this LSI outputs during ACK period, please must input 9 clocks.

*3 It is called R/W bit.

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